DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.

Intel and the Defense Advanced Research Projects Agency (DARPA), part of the U.S. Department of Defense, have entered into a multi-year, $49 million technology investment agreement to prototype revolutionary hardware and software technologies for extreme-scale computing systems as part of DARPA’s Ubiquitous High Performance Computing (UHPC) program.

/ Carter, Nicholas P.; Agrawal, Aditya; Borkar, Shekhar; Cledat, Romain; David, Howard; Dunning, Dave; Fryman, Joshua; Ganev, Ivan; Golliver, Roger A.; Knauerhase, Rob; Lethin, Richard; Meister, Benoit; Mishra, Asit K.; Pinfold, Wilfred R. Hp Compaq Dc7100 Ethernet Controller Driver Windows Xp. ; Teller, Justin; Vasilache, Nicolas; Venkatesh, Ganesh; Xu, Jianping. 19th IEEE International Symposium on High Performance Computer Architecture, HPCA 2013. Research output: Chapter in Book/Report/Conference proceeding › Conference contribution. Abstract = 'DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously. Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption.

Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture.' TY - GEN T1 - Runnemede T2 - An architecture for Ubiquitous High-Performance Computing AU - Carter,Nicholas P. AU - Agrawal,Aditya AU - Borkar,Shekhar AU - Cledat,Romain AU - David,Howard AU - Dunning,Dave AU - Fryman,Joshua AU - Ganev,Ivan AU - Golliver,Roger A.

AU - Knauerhase,Rob AU - Lethin,Richard AU - Meister,Benoit AU - Mishra,Asit K. Source Code Sistem Informasi Penjualan Dengan Php Dan Mysql Insert. AU - Pinfold,Wilfred R. AU - Teller,Justin AU - Torrellas,Josep AU - Vasilache,Nicolas AU - Venkatesh,Ganesh AU - Xu,Jianping PY - 2013/7/23 Y1 - 2013/7/23 N2 - DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously.

Near-threshold voltage operation, fine-grained power and clock management, and separate execution units for runtime and application code are used to reduce energy consumption. Memory energy is minimized through application-managed on-chip memory and direct physical addressing. A hierarchical on-chip network reduces communication energy, and a codelet-based execution model supports extreme parallelism and fine-grained tasks. We present an initial evaluation of Runnemede that shows the design process for our on-chip network, demonstrates 2-4x improvements in memory energy from explicit control of on-chip memory, and illustrates the impact of hardware-software co-design on the energy consumption of a synthetic aperture radar algorithm on our architecture. AB - DARPA's Ubiquitous High-Performance Computing (UHPC) program asked researchers to develop computing systems capable of achieving energy efficiencies of 50 GOPS/Watt, assuming 2018-era fabrication technologies. This paper describes Runnemede, the research architecture developed by the Intel-led UHPC team. Runnemede is being developed through a co-design process that considers the hardware, the runtime/OS, and applications simultaneously.